The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a heterojunction bipolar transistor.
Portable electronic devices, such as cellular phones, PDAs, DVCs, and DSCs, have become to be provided with a larger number of functions. Further, there are demands for compact and light products in the market. To satisfy such demands, highly integrated system LSIs are necessary.
One example of a module that realizes a high integration system LSI is a high frequency bipolar transistor. One example of a configuration for increasing the performance of a high frequency bipolar transistor is a silicon-germanium heterojunction bipolar transistor (SiGe HBT), which includes a base layer formed from silicon-germanium (SiGe).
Japanese Laid-Open Patent Publication No. 4-179235 describes a method for manufacturing a semiconductor device having a SiGe base heterojunction bipolar transistor, which is shown in FIG. 11. An enlarged view of an emitter-base region of the transistor is shown in FIG. 12.
Referring to FIG. 11, an n+ type collector embedment layer 101 is formed on a p− type silicon substrate (not shown). An n− type layer 102 (epitaxial layer), which functions as a collector layer, is epitaxially grown on the n+ type collector embedment layer 101. The n− type layer 102 is etched to remove portions excluding portions required for use as the collector layer and a collector extraction layer. A trench is formed in a device isolation region. A polycrystalline silicon film 104 is embedded in the trench via an oxide film 103. After the collector formation and device isolation region embedment, the substrate surface is flattened by an oxide film 105 (embedment oxide film). The oxide film 105 undergoes epitaxial growth to form a base and an emitter. More specifically, a p-type SiGe layer 106 (SiGe alloy layer), which functions as an internal base layer, is epitaxially grown. An n-type silicon layer 107, which functions as an emitter layer, and an n+ type silicon layer 108, which functions as an emitter-contact layer (emitter electrode), are epitaxially grown on the p-type SiGe layer 106. Then, the n+ type silicon layer 108 and the n-type silicon layer 107 are etched using an oxide film 109 as a mask to remove portions excluding portions required to form the emitter. The outer side of the region functioning as the internal base layer in the residual p-type SiGe layer 106 is etched for a predetermined depth using an oxide film 110 (side wall film) and the oxide film 109 as masks. This portion then undergoes selective epitaxial growth to form a p+ type SiGe layer 111, which functions as an external base layer.
In the SiGe base heterojunction bipolar transistor configuration of the prior art shown in FIG. 12, the n-type silicon layer 107, which functions as the emitter layer, is T-shaped and has a center projection (expansion portion). A contact surface 150 defined between the emitter layer 107 and the emitter electrode 108 is located at a position higher than a lower surface 160 of the side wall film 110. An emitter-base junction is formed at the lower side of the center projection. Accordingly, the width We2 of the portion corresponding to the emitter-base junction (width of emitter layer) is much greater than the width We1 of the n+ type silicon layer 108 (emitter electrode).
To manufacture a semiconductor device (SiGe base heterojunction bipolar transistor) that has higher performance with the prior art configuration, the n+ type silicon layer 108 (emitter electrode) must further be processed in a miniaturized manner to decrease the width We1, which would further decrease the width We2 of the emitter layer. However, this would result in the need of a highly accurate exposure apparatus and thus increase manufacturing costs.